(A) Field of the Invention
The present invention is related to a programming method and a manufacturing method for non-volatile memory, and more particularly to a programming method and a manufacturing method for split gate memory.
(B) Description of the Related Art
Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim (F-N) tunneling.
In IEDM Conference 2002, Y. Sasago et al. disclosed a formation process of a split gate memory as shown in FIGS. 1(a) through 1(e), wherein U-shaped floating gates are used for reducing threshold voltage (Vth) shift. In FIG. 1(a), a gate oxide layer 11, a polysilicon layer 12 and a silicon oxide layer 13 are sequentially formed on a silicon substrate 10, and patterned by lithography and etching processes to form separated lines. In FIG. 1(b), oxide spacers 14 are formed by oxide deposition and etching, or thermal growth. Then, dopants such as arsenic ions are implanted with a tilted angle to form n+ regions 15. In FIG. 1(c), because doped silicon usually has a relatively high oxide growth rate in comparison with that of undoped silicon, a tunnel oxide layer 16 with a thicker portion 17 on the n+ regions 15 can be formed by thermal growth. Then, a polysilicon layer 18 is deposited, and polymer plugs 19 are deposited in the spaces between the polysilicon lines 12 as etch-back masks. In FIG. 1(d), the polysilicon layer 18 is etch-backed to be separated floating gates. In FIG. 1(e), the polymer plugs 19 are removed, and then an oxide/nitride/oxide (ONO) layer 20 and a polysilicon layer 21 are deposited. Then, the polysilicon layer 21 is patterned to be separated wordlines, i.e., control gates. Accordingly, in addition to the polysilicon layers 18 and polysilicon layer 21 function as floating gates and control gate respectively, the polysilicon lines 12 serve as select gates.
Referring to FIG. 2, U.S. Pat. No. 6,567,315 disclosed an operation method for a split gate memory cell, which can be applied to the memory cells disclosed by Sasago et al. Accordingly, the polysilicon layers 12, 18 and 21 described above are denoted by SG, FG and CG, and doping regions 15 act as source (S) and drain (D). Voltages of approximately 14V, 5V and 0.6V are applied to the control gate CG, drain D and select gate SG respectively, and source S is grounded. Consequently, a depletion region is formed within the substrate and a drain current is generated thereby, and therefore hot electrons generated when a drain current flows from the source side to the drain side are injected into the floating gate FG for programming, that is, the so-called hot electron programming.
Moreover, Yamauchi et al. disclosed a process for forming a split gate memory cell in the International Conference on Solid State Devices Materials, Yokohama, 1994. In FIG. 3(a), gate structures with a tunnel oxide layer 301, a floating gate 302, an ONO layer 303, a control gate 304 and a silicon dioxide layer 305 are formed on a substrate 30, and photoresist 306 is patterned to cap a portion of the substrate 30. Then, the substrate 30 uncovered by the photoresist 306 is implanted by dopants such as arsenic ions, so as to form a drain region 307. In FIG. 3(b), the photoresist 306 is stripped, a polysilicon layer 309 is deposited, and then silicon oxide spacers 310 are formed. Sequentially, another implantation is conducted to form source region 311. In FIG. 3(c), a tungsten silicide layer 312 is deposited after the silicon oxide spacers 310 are removed, and then the tungsten silicide layer 312 is etched to define the select gate.
Apparently, the above prior art references are either complex processes or limited to the operation by hot electron programming, so that an alternative process and operation method are needed to enhance the production efficiency and obtain better operation flexibility.